Semiconductor devices are essential elements in producing electronic products. Updates of the semiconductor devices have been a driving force for development of semiconductor technologies and progress of semiconductor industry, especially for elevation of the performance of central processing units (CPU) and memories. Since the end of the last century, the process for manufacturing chips has been developed rapidly, the level of which has been increased from micrometer level to less than 32 nm.
Under the background that photolithography technologies have a limitation to be further improved, as well as advanced photolithography technologies are impossible to be used to achieve a mass production, continually reducing sizes of minimum patterns would imply a constant increase of the cost and a decrease of the yield. At present, taking a 32 nm planar transistor technology as an example, which has reached to a technology limitation, various serious short-channel effects may be introduced, and meanwhile a raising of an off-state current and a lowering of a transconductance, etc. of the planar transistor may be caused. When a new process is about to be put into use, tests for reliability of gate dielectric of a semiconductor device manufactured by such process become an important subject. Since electron traps and hole traps in the gate dielectric layer of the semiconductor device, i.e. certain dangling bonds or socalled defects, would cause a drift of a threshold voltage of the semiconductor device and a decrease of an on-state current, thus resulting in a serious negative/positive bias temperature instability (NBTI/PBTI), and at the same time would cause an increase of a gate-drain current to decrease the reliability and the life span of the semiconductor device, researches and tests on the traps in the dielectric layer may provide an optimal solution for manufacturing the device, and tests of reliability with respect to traps is one of the important manners for characterizing the life span of the semiconductor device.
A relatively precise method for testing traps for conventional planar transistor devices is a charge pump test. However, the method cannot be used in a semiconductor device that has an ultra-small area. As to a novel device, such as a 32 nm device using a bulk silicon process, there is an effective channel area of less than 0.002 square micrometers. In other words, in an advanced process condition, the number of traps in each semiconductor device is smaller. If the charge pump test for the conventional planar transistor device is used, the test can be only performed on relatively large devices. However, the actual situation of the traps in the ultra-small devices cannot be represented. Further, if the charge pump test is directly performed on the ultra-small devices, there may be a substantial error in the test result. Therefore, the traditional charge pump test can not be used in the present novel device, especially in the process under 22nm. Currently, the test of the number/density/location of the traps in the gate dielectric layer of the ultra-small device has become a focus issue in manufacturing integrated circuits.